1. Field of the Invention
The present invention relates to design technology of semiconductor integrated circuits and, more particularly, to an automatic circuit design apparatus, a method for automatically designing a circuit, a computer program product for executing an application for an automatic circuit design apparatus, for designing a circuit capable of decreasing leakage current of complementary metal-oxide-semiconductor (CMOS) transistors.
2. Description of the Related Art
A decrease in the threshold voltage of transistors progresses in proportion to a decrease in size of semiconductor integrated circuits and voltage value of the supply voltage. By the decrease in the threshold voltage, the leakage current of CMOS transistors increases. For power consumption limited equipment, such as mobile communication equipment, the increase of the leakage current becomes a serious problem. In order to decrease the leakage current, a technique has been proposed to configure a logic circuit by cells consisting of low-threshold-voltage transistors (hereinafter referred to as “low-threshold cells”), and to place switch cells between the low-threshold cells and a ground. Since the low-threshold cells can operate at a high speed, it is possible to reduce a path delay time.
Although the low-threshold cells can operate at a high speed, the leakage current quantity becomes large because the low-threshold cells are turned on by a small input voltage. On the other hand, cells composed of high-threshold-voltage transistors (hereinafter referred to as “high-threshold cells”), compared to the low-threshold cells, generate a small leakage current but operate at a low speed. The leakage current from the low-threshold cells is shut out because the switch cells go to an off state during a standby period. The switch cells go to an on state during a period of normal operation.
During the period of normal operation, the electric current at a ground goes to a maximum quantity when output signals of cells are changed to a low level. Accordingly, when many low-threshold cells are connected to a switch cell, a large electric current flows to the switch cell. When the large electric current flows to the switch cell, the discharge time of the electric current increases by on-resistance of the switch cell. As a result, since the output signals of the low-threshold cells connected to the switch cell does not go to a low level rapidly, the delay time of the low-threshold cells increases. Therefore, a path delay analysis taking into consideration the delay time caused by the increase of the discharge time of the low-threshold cells (hereinafter referred to as “a discharge delay”) is required. The path delay analysis which considers the discharge delay requires a long time compared to normal path delay analysis. Although the discharge time can be reduced by increasing a switch cell area, the circuit scale of a designed circuit increases.